1. Field of the Invention
This invention relates to testing of dice on a wafer, and in particular to reducing the testing of dice with on-chip identification of good dice.
2. Description of the Related Art
Wafer sorting is a well-known process performed after wafer fabrication. During wafer sorting, each die on the wafer is electrically tested for electrical performance and circuit functioning. Thus, wafer sorting provides information on the effectiveness of the wafer fabrication process in producing working dice (i.e. chips) and provides identification of working dice which will be used in a subsequent packaging process.
FIGS. 1A and 1B show a typical wafer sort process including testing of all dice during a second sort. As is well-known to those in the art, each die typically includes a plurality of memory cells, in this example electrically programmable read only memory (EPROM) cells. An EPROM cell includes a source and a drain region separated by a channel region. A floating gate is formed over the channel region, while a control gate is formed over the floating gate. Referring to FIGS. 1A and 1B, all memory cells on a die are programmed in step 11 by varying the charge on the floating gate, thereby changing the threshold voltage required to allow a current to flow between the source and drain regions.
In step 12, the programming of the memory cells on the die is verified with a probe to ensure all memory cells exhibit an appropriate threshold voltage. If any of the memory cells on the die fail to exhibit the appropriate threshold voltage, then a number in a counter increments to indicate that a programming attempt has occured. This number in the counter is compared to a predetermined, maximum number of attempts set by the tester. If the number in the counter is less than or equal to the predetermined maximum number, all the memory cells on the die are reprogrammed. For simplicity, this comparing and reprogramming is included in verification step 12. Step 12 is typically repeated until either all the memory cells are satisfactorily programmed, or until the predetermined maximum number of attempts has been exceeded. At this time, if the die is "good" (i.e. all the memory cells exhibit the appropriate threshold voltage) as determined in step 13, the die is electronically inked. Electronic inking is a well-known method in the art in which one or more memory cells on the die are programmed to indicate a particular testing pattern for the probe in the second wafer sort (described below). If the die is "bad" (as determined in step 13) or after the probe programs and verifies the electronic inking of the die (as performed in step 14), the probe determines in step 15 if that die is the last die on the wafer. If that die is not the last die, the probe proceeds to the next die in step 16. However, if that die is the last die, then the probe proceeds in step 18 to the next wafer (if identified in step 17). Steps 11-18 constitute the first wafer sort 10.
After first wafer sort 10 is completed, the wafers are placed under predetermined, adverse conditions 20 to accelerate charge loss, thereby simulating memory use over, for example, a twenty year period. Typically, these predetermined, adverse conditions include baking the wafers as shown in step 21.
Second wafer sort 30 begins in step 31 by reading a first die for electronic ink. If the die is electronically inked, as determined in step 32, the probe tests the memory cells on the die in step 33 to determine the degree of charge loss. If the charge loss of a particular die exceeds a predetermined level as determined in step 34, that die is physically inked in step 37 (indicating the die is rejected for packaging). If, on the other hand, the charge loss is less than or equal to that predetermined level (i.e. the die is "good" and is ready to be used in the subsequent packaging process), then the probe determines if another die is present in step 35. If another die is present, the probe proceeds to the next die in step 36. Steps 31-37 are repeated until the last die on the wafer is found. Then, the probe moves to the next wafer in step 39 (if determined to be present in step 38). Otherwise, the probe stops in step 40.
This conventional method includes unnecessary testing time because all dice, whether or not successfully programmed in first wafer sort 10 (i.e. determined to be good or bad) are read for electronic ink in second wafer sort 30. Therefore, a need arises for a method of reducing the test time of dice on a wafer.